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<title>DIVSD—Divide Scalar Double-Precision Floating-Point Value </title></head>
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<h1>DIVSD—Divide Scalar Double-Precision Floating-Point Value</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>F2 0F 5E /r DIVSD xmm1, xmm2/m64</td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Divide low double-precision floating-point value in xmm1 by low double-precision floating-point value in xmm2/m64.</td></tr>
<tr>
<td>VEX.NDS.128.F2.0F.WIG 5E /r VDIVSD xmm1, xmm2, xmm3/m64</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Divide low double-precision floating-point value in xmm2 by low double-precision floating-point value in xmm3/m64.</td></tr>
<tr>
<td>EVEX.NDS.LIG.F2.0F.W1 5E /r VDIVSD xmm1 {k1}{z}, xmm2, xmm3/m64{er}</td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Divide low double-precision floating-point value in xmm2 by low double-precision floating-point value in xmm3/m64.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Divides the low double-precision floating-point value in the first source operand by the low double-precision floating-point value in the second source operand, and stores the double-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 64-bit memory location. The first source and destination are XMM registers.</p>
<p>128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-1:64) of the corresponding ZMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The quadword at bits 127:64 of the destination operand is copied from the corresponding quadword of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.</p>
<p>EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The quadword element of the destination operand at bits 127:64 are copied from the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.</p>
<p>EVEX version: The low quadword element of the destination is updated according to the writemask.</p>
<p>Software should ensure VDIVSD is encoded with VEX.L=0. Encoding VDIVSD with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.</p>
<h2>Operation</h2>
<p><strong>VDIVSD (EVEX encoded version)</strong></p>
<pre>IF (EVEX.b = 1) AND SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN
              DEST[63:0] (cid:197) SRC1[63:0] / SRC2[63:0]
    ELSE
         IF *merging-masking*
                                                    ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE
                                                    ; zeroing-masking
                    THEN DEST[63:0] (cid:197) 0
         FI;
FI;
DEST[127:64] (cid:197) SRC1[127:64]
DEST[MAX_VL-1:128] (cid:197) 0</pre>
<p><strong>VDIVSD (VEX.128 encoded version)</strong></p>
<pre>DEST[63:0] (cid:197)SRC1[63:0] / SRC2[63:0]
DEST[127:64] (cid:197)SRC1[127:64]
DEST[MAX_VL-1:128] (cid:197)0</pre>
<p><strong>DIVSD (128-bit Legacy SSE version)</strong></p>
<pre>DEST[63:0] (cid:197)DEST[63:0] / SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VDIVSD __m128d _mm_mask_div_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);</p>
<p>VDIVSD __m128d _mm_maskz_div_sd( __mmask8 k, __m128d a, __m128d b);</p>
<p>VDIVSD __m128d _mm_div_round_sd( __m128d a, __m128d b, int);</p>
<p>VDIVSD __m128d _mm_mask_div_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);</p>
<p>VDIVSD __m128d _mm_maskz_div_round_sd( __mmask8 k, __m128d a, __m128d b, int);</p>
<p>DIVSD __m128d _mm_div_sd (__m128d a, __m128d b);</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal</p>
<h2>Other Exceptions</h2>
<table class="exception-table">
<tr>
<td>VEX-encoded instructions, see Exceptions Type 3.</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E3.</td></tr></table></body></html>